/*
 * Copyright (C) 2017-2020 Alibaba Group Holding Limited
 */

/******************************************************************************
 * @file     dw_gpio_ll.h
 * @brief
 * @version
 * @date     2020-01-07
 ******************************************************************************/

#ifndef _DW_GPIO_H_
#define _DW_GPIO_H_

#include <soc.h>
#include <csi_core.h>

#ifdef __cplusplus
extern "C" {
#endif

/* IS_SYNC, offset: 0x60 */
#define DW_GPIO_IS_SYNC_SYNC_LEVEL_Pos             (0U)
#define DW_GPIO_IS_SYNC_SYNC_LEVEL_Msk             (0x1U << DW_IIC_CON_MASTER_Pos)
#define DW_GPIO_IS_SYNC_SYNC_LEVEL                 DW_GPIO_IS_SYNC_SYNC_LEVEL_Msk


typedef struct {
    __IOM uint32_t SWPORTA_DR;                    /* Offset: 0x000 (W/R)  PortA data register */
    __IOM uint32_t SWPORTA_DDR;                   /* Offset: 0x004 (W/R)  PortA data direction register */
    __IOM uint32_t PORTA_CTL;                     /* Offset: 0x008 (W/R)  PortA source register */
    __IOM uint32_t RESERVED1[9];                  /* Offset: 0x028 (W/R)  Reserve register */
    __IOM uint32_t INTEN;                         /* Offset: 0x000 (W/R)  Interrupt enable register */
    __IOM uint32_t INTMASK;                       /* Offset: 0x004 (W/R)  Interrupt mask register */
    __IOM uint32_t INTTYPE_LEVEL;                 /* Offset: 0x008 (W/R)  Interrupt level register */
    __IOM uint32_t INT_POLARITY;                  /* Offset: 0x00c (W/R)  Interrupt polarity register */
    __IM  uint32_t INTSTATUS;                     /* Offset: 0x010 (R)    Interrupt status of Port */
    __IM  uint32_t RAWINTSTATUS;                  /* Offset: 0x014 (W/R)  Raw interrupt status of Port */
    __IOM uint32_t RESERVED2;                     /* Offset: 0x018 (W/R)  Reserve register */
    __OM  uint32_t PORTA_EOI;                     /* Offset: 0x01c (W/R)  Port clear interrupt register */
    __IM  uint32_t EXT_PORTA;                     /* Offset: 0x020 (W/R)  PortA external port register */
    __IOM uint32_t RESERVED3[3];                  /* Offset: 0x028 (W/R)  Reserve register */
    __IOM uint32_t LS_SYNC;                       /* Offset: 0x030 (W/R)  Level-sensitive synchronization enable register */
} dw_gpio_regs_t;

static inline void dw_gpio_write_output_port(dw_gpio_regs_t *port, uint32_t value)
{
    port->SWPORTA_DR = value;
}

static inline uint32_t dw_gpio_read_output_port(dw_gpio_regs_t *port)
{
    return port->SWPORTA_DR;
}

static inline void dw_gpio_set_port_direction(dw_gpio_regs_t *port, uint32_t value)
{
    port->SWPORTA_DDR = value;
}

static inline uint32_t dw_gpio_read_port_direction(dw_gpio_regs_t *port)
{
    return port->SWPORTA_DDR;
}

static inline void dw_gpio_set_port_source(dw_gpio_regs_t *port, uint32_t value)
{
    port->PORTA_CTL = value;
}

static inline uint32_t dw_gpio_read_port_source(dw_gpio_regs_t *port)
{
    return port->PORTA_CTL;
}

static inline void dw_gpio_set_port_irq(dw_gpio_regs_t *port, uint32_t value)
{
    port->INTEN = value;
}

static inline uint32_t dw_gpio_read_port_irq(dw_gpio_regs_t *port)
{
    return port->INTEN;
}

static inline void dw_gpio_set_port_msk(dw_gpio_regs_t *port, uint32_t value)
{
    port->INTMASK = value;
}

static inline uint32_t dw_gpio_read_port_msk(dw_gpio_regs_t *port)
{
    return port->INTMASK;
}

static inline void dw_gpio_set_port_irq_sensitive(dw_gpio_regs_t *port, uint32_t value)
{
    port->INTTYPE_LEVEL = value;
}

static inline uint32_t dw_gpio_read_port_irq_sensitive(dw_gpio_regs_t *port)
{
    return port->INTTYPE_LEVEL;
}

static inline void dw_gpio_set_port_irq_polarity(dw_gpio_regs_t *port, uint32_t value)
{
    port->INT_POLARITY = value;
}

static inline uint32_t dw_gpio_read_port_irq_polarity(dw_gpio_regs_t *port)
{
    return port->INT_POLARITY;
}

static inline uint32_t dw_gpio_read_port_int_status(dw_gpio_regs_t *port)
{
    return port->INTSTATUS;
}

static inline uint32_t dw_gpio_read_raw_port_int_status(dw_gpio_regs_t *port)
{
    return port->RAWINTSTATUS;
}

static inline void dw_gpio_clr_port_irq(dw_gpio_regs_t *port, uint32_t value)
{
    port->PORTA_EOI = value;
}

static inline uint32_t dw_gpio_read_input_port(dw_gpio_regs_t *port)
{
    return port->EXT_PORTA;
}

static inline void dw_gpio_set_sync_level(dw_gpio_regs_t *port, bool enable)
{
    port->LS_SYNC = enable;
}

static inline uint32_t dw_gpio_read_sync_level(dw_gpio_regs_t *port)
{
    return port->LS_SYNC;
}


#ifdef __cplusplus
}
#endif

#endif

